1. Field of the Invention
The present invention relates to an integrated circuit having improved electrostatic discharge (ESD) protection.
2. Description of the Prior Art
In the design of integrated circuits, the problem of ESD protection has received considerable attention, especially as dimensions shrink below the 1.5 micron level. In addition, the lightly doped drain (LDD) type transistor structure is suspected of reducing the voltage threshold at which ESD failure occurs. An excessively high ESD voltage conducted from a package terminal to the integrated circuit bondpad can easily damage input or output circuitry, unless protection techniques are adopted. Some approaches to improving ESD performance rely on the use of voltage-clamping diodes or transistors. For example, referring to FIG. 1, an input/output bondpad 100 is connected to a package terminal. An output stage (transistors 101, 102) and/or an input stage (transistors 108, 109) are coupled to the bonded. Typically, protection devices 103 and 104 limit the voltage on the bondpad. The input resistor 105 and additional diodes 106, 107 are also optionally provided in some cases, to further protect the input transistors. When the n-channel output transistor 102 is present, experience indicates that it often breaks down at a lower voltage than the protection circuitry, due to its inherent bipolar action through the source/substrate/drain path.
The voltage-clamping techniques are especially desirable to protect the input transistors, where breakdown of the thin gate oxide is a very significant source of failure due to ESD events. Various voltage clamping device structures have been adopted to improve ESD protection; see, for example, U.S. Pat. Nos. 4,806,999 and 4,821,089 co-assigned herewith.
Another approach to ESD protection is to supply a capacitance across the power supply voltage conductors (V.sub.DD and V.sub.SS); see "The Dynamics of Electrostatic Discharge Prior to Bipolar Action Related Snap-Back"; G. Krieger, 1989 EOS/ESD Symposium Proceedings. This is said to provide increased protection by slowing down the increase of the voltage on the input/output bondpad during an ESD event. That is said to provide additional time for the ESD protection circuitry to react, thereby protecting the thin gate oxides that are very susceptible to ESD damage. However, the capacitance relied on for this purpose is the n-well to PG,3 p-substrate junction capacitance that is formed by the n-well in which p-channel transistors are formed. It is also noted in the Krieger article that the capacitance is charged via a forward biased p+ drain to n-well diode, being diode D.sub.p shown in FIG. 2 of Krieger.